1. Field of the Invention
The invention disclosed and claimed herein generally pertains to a method and apparatus for improving performance of a configuration comprising a bus controller and master and slave devices connected thereto. More particularly, the invention pertains to a method and apparatus of the above type, wherein multiple slave devices are simultaneously connected to a single interface of the controller, and command to command pipelining is used with at least one of the multiple slave devices. Even more particularly, the invention pertains to a method and apparatus of the above type, wherein specified mechanisms are added to the bus controller and also to the master and slave devices, in order to achieve the above goals.
2. Description of the Related Art
As is known by those of skill in the art, buses are used in applications such as system-on-a-chip, as well as other applications, to interconnect a variety of devices such as processors, memories, and I/O devices. These buses have bus controllers, which are used to interconnect active devices that include both master and slave devices, so that the active devices can communicate with one another. Some types of bus controllers have one or more interfaces for master devices, and also have one or more other interfaces for the slave devices. Each interface comprises a dedicated set of pins or wires, which can be attached to either a master or a slave device depending on the type of interface. In some typical arrangements, a bus controller has eight or twelve dedicated master interfaces, and can thus support eight or twelve master devices, respectively.
Commands to transfer data, also known as requests, originate within a master device, are sent to one or more slave devices, and are then acknowledged or responded to by the slave devices. A command typically includes the address of the intended slave recipient, the length of the transaction and whether the transaction is a read or write request. Generally, a read request causes data to be read from a slave to the master, and a write request causes data to be written to a slave from the master. Slaves generally acknowledge the commands with either an acceptance, a retry, or an error message. As used herein, an acceptance indicates that the slave recipient of a command is able to comply and will do so. A retry indicates that the slave is not able to carry out the request at the time that the command is received, so that the command should be retried or re-sent later.
It is often desirable to allow multiple slaves to be attached to a common, or the same, slave interface of a bus controller. Most signals sent from the bus controller to the slave devices, such as address and write data, are then multi-dropped. That is, the signals are broadcast to all slaves connected to the common interface, even though only one slave will respond to the signals. Similarly, most signals from multiple slaves attached to a common interface are grouped together in an OR arrangement. That is, they are all connected to the controller interface through a common read data bus. Data is read from only one slave device at any one time, while the other slaves remain inactive. Thus, the output of the read data bus is determined only by the input provided by the active slave, similar to the operation of an OR gate.
An important advantage in attaching multiple slaves to a single slave interface is that the bus controller can support a large number of slaves, without requiring extensive resources in terms of bus controller area and power. In one configuration, performance is managed by arranging high performance slaves to each use a unique, individual interface to the bus controller, while arranging the lower performance slaves to share a common interface. Notwithstanding the advantages of this configuration, however, prior art bus controllers that attach multiple slave devices to a single slave interface generally cannot support command to command pipelining. Herein, a command is initiated when it is sent from a master device to one of the slave devices. A command is completed when a response acknowledging the command has been received back by the master device. As used herein, the terms “pipelining”, “command pipelining” and “command to command pipelining” all refer to a procedure wherein a master device is allowed to initiate or send out a command before a response acknowledging a previously initiated command (and which completes the previous command) has been delivered back to the sender. Command pipelining clearly improves performance, by reducing time requirements in comparison with systems that must wait for a command to be acknowledged before the next command can be sent. Thus, it would be desirable to support command pipelining in a bus controller and its connected devices, while at the same time supporting connection of multiple slaves to a single slave interface.